Programmable Digital Electronics and Systems Lab - PRODIGIESLAB LLC
CMOS APS camera
Designed the FPGA-based testbench for testing and characterization. VLSI design and tape out from Jiawei Friedrich Xu.
My first tape-out
Two structures of 4-transistors APS unitcell designed to test, characterize and compare the n+/p-sub and the n+/n-well/p-sub (W on image) architectures.
​A Readout Integrated Circuit (ROIC) with hybrid source/sensor array
(Bottom left) Based on test results of a conventional Readout Integrated Circuit (ROIC) with basic light detecting function, this chip proposed a new design, which integrates a dense addressable light emitting LED and photo detector array, with on-chip control, driver electronics and improved performance [Read more].
Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing
A new 96 × 96 array of 30 μm × 30 μm readout integrated circuit (ROIC) with an individual pixel tunable bias control is demonstrated.
Detailed IC design, test structures, readout circuit building blocks, and applied techniques are discussed.
The new ROIC is capable of providing a large voltage swing for the bias in both positive and negative polarities to each individual pixel, independently.
These enhanced functionalities are achieved by modifying a capacitive transimpedance amplifier (CTIA) CMOS ROIC architecture.
An FPGA-based test bench has also been developed to test and characterize the new ROIC system, for which software and hardware are described in detail.
The test chip has been fabricated with 2P4M 0.35 μm high-voltage CMOS technology, where the bias voltage range is ±5 V and the output swing range is ±3.9 V.
The demonstrated ROIC is an ideal infrastructure for implementation of region of interest enhancement, a solid base for infrared multispectral acquisition targeting an infrared retina, and high-resolution 2D in vitro neural interface for simultaneous bio-stimulation and measurement. [Read more].
Test ROIC for Situational Awareness WISP @ Copious Imaging/Anduril Industries
ASIC/ DI-BDI IR ROIC design in CMOS SkyWater 90nm, TSMC 22nm PDK.
Design of custom low power, high-speed, small area, digital-in-pixel unitcell, DFF, SRAM, Mux, OpAmp, ADC, Binary/Gray code counters, SerDes, CML;
RTL, schematics, simulation, floor-planning on Cadence Virtuoso, DRC, PEX, LVS verification on Mentor Calibre;
Monte Carlo, power analysis, clock distribution, timing constraints, DFT, STA, ESD-Pad.
Tapeout, cryogenic testing, and characterization with VHDL/FPGA control;
LiDAR front-end R-TIA design and simulation;
Design, simulation, proposal, and further adoption of new front-end buffer and digital mux architecture.